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NIS1050 Protection Interface Circuit for PMICs with Integrated OVP Control
The NIS1050 is a protection IC targeted at the latest generation of PMICs from the leading mobile phone and UMPC chipset vendors. It includes a highly stable low-current LDO and a low impedance power N-Channel MOSFET. The LDO provides a low current, five volt supply to the PMIC, and the NFET is the external pass element for the OVIC circuit. These stages combine with the internal PMIC to protect the charging circuit from low-impedance overvoltage conditions that can occur from either the AC/DC or USB supply. The NIS1050 is available in the low-profile 6-lead 2x2mm WDFN6 surface mount package.
Features http://onsemi.com MARKING DIAGRAMS
1 WDFN6, 2x2 CASE 506AN PM M
PM = Specific Device Code M = Date Code
* Lower Power Dissipation and Higher Efficiency vs. Zener Shunt * * *
Regulator LDO Highly Stable across Temperature, Operates Without Bypass Capacitors Wide 3-30 V Power Supply Voltage Input Range Low-Profile (0.75mm) 6-Lead 2x2mm WDFN6 Package
ORDERING INFORMATION
Device NIS1050MNTBG Package WDFN6 (Pb-Free) Shipping 3000 / Tape & Reel
Typical Applications
* Power Interface for New Generation PMICs from Leading Mobile
Phone and UMPC Chipset Vendors
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
PMIC
OVP_SNS
3,7 6,8 2 Vbus USB
NIS1050 LDO 1 4
VCHG VCHG
2
Voltage Detector V_REF_2 V_REF_1
V_IN_OKAY LDO
5
OVP_CLAMP
Bandgap Reference
OVP_CTL
other control inputs
4 Controller
A) If okay, FET is closed B) If not okay, FET is opened
10k
4.7uF
Vout, OUTPUT VOLTAGE (V)
3
Over-Voltage Protection
5.30 5.25 5.20 5.15 5.10 5.05 5.00 4.95 4.90 4.85 4.80 -40 -15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
Figure 1. Typical Application
Figure 2. Output Voltage Variation with Temperature
(c) Semiconductor Components Industries, LLC, 2009
July, 2009 - Rev. 0
1
Publication Order Number: NIS1050/D
NIS1050
1 2 3 7 8 6 5 4
Figure 3. Pin Assignment Table 1. FUNCTIONAL PIN DESCRIPTION
Pin 1 2 3, 7 4 5 6, 8 Function Source Gate Vin Ground Vout Drain Description This is the source of the power FET and connects to the PMIC pin of the same name. This pin is the gate of the FET switch. Positive input voltage to the device. Negative input voltage to the device. This is used as the internal reference for the IC. This is the output of the internal LDO. It passes the input voltage through to the output and clamps that voltage if it exceeds the regulation limit. Positive input voltage to the device.
MAXIMUM RATINGS
Rating Input Voltage, Operating, Steady-State (OVP_sense to Gnd) Gate-to-Source Voltage Drain Current, Peak (10 ms pulse) Drain Current, Continuous (Note 1, Steady-State) TA = 25C TA = 85C Total Power Dissipation @ TA = 25C (Note 1, 2) Operating Temperature Range Non-operating Temperature Range Maximum Lead Temperature for Soldering Purposes Symbol Vin VGS IDpk ID 3.7 2.7 Pmax TJ TJ TL 750 -40 to 125 -55 to 150 260 mW C C C Value -0.3 to 30 8 20 Unit V V A A
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface Mounted on FR4 Board using the minimum recommended pad size of 30 mm2, 2 oz Cu. 2. Dual die operation (equally-heated).
THERMAL RESISTANCE RATINGS
Parameter SINGLE DIE OPERATION (SELF-HEATED) Junction-to-Ambient - Steady State (Note 3) Junction-to-Ambient - Steady State Min Pad (Note 4) Junction-to-Ambient - t 5 s (Note 3) DUAL DIE OPERATION (EQUALLY-HEATED) Junction-to-Ambient - Steady State (Note 3) Junction-to-Ambient - Steady State Min Pad (Note 4) Junction-to-Ambient - t 5 s (Note 3) RqJA RqJA RqJA 58 133 40 C/W RqJA RqJA RqJA 83 177 54 C/W Symbol Max Unit
3. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 4. Surface Mounted on FR4 Board using the minimum recommended pad size (30 mm2, 2 oz Cu).
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NIS1050
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: Vcc (OVP_sense) = 5.0 V, TJ = 25C)
Characteristics POWER FET Zero Gate Voltage Drain Current (VDS = 24 Vdc, VGS = 0 V) TJ = 85C Gate-to-Source Leakage Current (VDS = 0 V, VGS = 8 V) Gate Threshold Voltage (VGS = VDS, ID = 250 mA) Negative Gate Threshold Temperature Coefficent Drain-to-Source On-Resistance (Note 5) VGS = 4.5 V, ID = 2.0 A VGS = 2.5 V, ID = 2.0 A Forward Transconductance (VDS = 5 V, ID = 2.0 A) Input Capacitance (VDS = 15 Vdc, VGS = 0 Vdc, f = 1 MHz) Output Capacitance (VDS = 15 Vdc, VGS = 0 Vdc, f = 1 MHz) Reverse Transfer Capacitance (VDS = 15 Vdc, VGS = 0 Vdc, f = 1 MHz) LDO (Unless otherwise noted, TJ = 25C, Vin = 5.0 V) Regulated Output Voltage (Vcc = 5.5 V Io = 1 mA) Response to Input Transient (Vin 0 to 30 volts, <1 ms rise time, 5.0 kW resistive load, Note 6) Time for signal above 5.5 volts Peak Voltage Headroom (Vin - Vout, Iout = 1.2 mA, Vin = 4.6 V) Headroom (Vin - Vout, Iout = 10 mA, Vin = 4.8 V, TJ = -40 to 125C) TOTAL DEVICE Input Bias Current Minimum Operating Voltage 5. Pulse test: Pulse width 300 ms, duty cycle 2%. 6. Guaranteed by design. Ibias Vin-min 110 850 3.0 mA V Vout 4.6 5.0 5.3 V IDSS IGSS VGS(th) VGS(th)/TJ RDS(on) gFS CISS COSS CRSS 0.4 0.7 2.8 47 56 4.5 427 51 32 70 90 S pF pF pF 1.0 10 100 1.0 mA nA V mV/C mW Symbol Min Typ Max Unit
tpulse Vpk Vhead Vhead
5.0 9.0 150 1000
ms V mV mV
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NIS1050
TYPICAL PERFORMANCE CURVES
VGS = 1.7 V to 8 V TJ = 25C 1.6 V 4 3 2 1 0 1.5 V 1.4 V 1.3 V 1.2 V 0 1 2 3 4 5 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 5 ID, DRAIN CURRENT (AMPS) 1.6 1.4 1.2 1.0 0.8 0.6 -50 ID = 2 A VGS = 4.5 V
-25
0
25
50
75
100
125
150
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
TJ, JUNCTION TEMPERATURE (C)
Figure 4. On-Region Characteristics
Figure 5. On-Resistance Variation with Temperature
5.30 5.25 Vout, OUTPUT VOLTAGE (V) 5.20 5.15 5.10 5.05 5.00 4.95 4.90 4.85 4.80 -40
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
Figure 6. Output Voltage Variation with Temperature Mounting Considerations
The LDO and MOSFET are both attached to thermal pads to provide a low impedance path for the heat generated in these devices. Both of these pads should have a solid connection to as much board copper area as possible in order to maintain a low operating temperature. The main purpose of both of these pads is for thermal connections, not electrical connections. Pad 7 is the input voltage for the LDO. It is electrically connected to the Vcc pin. This connection is optional and will have a negligible difference in the electrical performance of the chip due to the current into the LDO. Pad 8 is the drain of the power MOSFET. This pad will also have a low electrical impedance. Either pad 8, pad 6 or both may be used for electrical connections. The total
impedance of the FET will not vary significantly since pad 6 is part of the lead-frame and therefore connected to pad 8 by a metal path on the lead frame. The majority of the package impedance comes from the resistance between the source and pin 1, since this is connected by bond wires.
Bypass Capacitors
The LDO has been designed to operate in a stable mode without bypass capacitors; however, it is recommended to use a low ESR capacitor if fast, ac transients or other switching type currents will be present. Typically, a value of 1 to 10 nF is adequate for an output bypass capacitor. A 1 nF capacitor may be added to the input if the input source is noisy or if it has a high ac impedance due to long trace lengths.
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NIS1050
PACKAGE DIMENSIONS
WDFN6, 2x2 CASE 506AN-01 ISSUE D
D A B
EXPOSED Cu MOLD CMPD NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e F K L L1 MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.25 0.35 2.00 BSC 0.57 0.67 2.00 BSC 0.90 1.10 0.65 BSC 0.15 BSC 0.25 REF 0.20 0.30 --0.10
PLATING
0.10 C 0.10 C
0.10 C 0.08 C
NOTE 4
D2 L
1 3
DETAIL A
K e
The products described herein (NIS1050), may be covered by one or more U.S. patents.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
II II II
DETAIL B 6
PIN ONE REFERENCE
DETAIL B
E
OPTIONAL CONSTRUCTIONS
L L1 A3 A A1 C
SEATING PLANE OPTIONAL CONSTRUCTIONS
TOP VIEW
DETAIL A
SIDE VIEW
0.10 C A D2 F
B
E2
0.10 C A
B
PACKAGE OUTLINE
4
6X
b 0.10 C A 0.05 C B
6X
NOTE 3
BOTTOM VIEW
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5
EE CC
L
6X
CCC EEE EEE
SOLDERMASK DEFINED MOUNTING FOOTPRINT
1.74 0.77 1.10 0.47 2.30
2X
1 0.35
0.65 PITCH
DIMENSIONS: MILLIMETERS
NIS1050/D

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